L3GO (Layout using Gridded Glyph Geometry Objects) is an ongoing project for improving the manufacturability of VLSI designs. L3GO provides a restricted set of objects or patterns that describes circuit connectivity and devices, referred to as glyphs. L3GO has three types of glyphs, including:
1. Stick glyphs, which are 1-dimensional line segments drawn between two grid points, e.g., used to describe FET gates or for interconnections. The attached properties of a stick glyph include which layer the stick belongs to, the start and end point, and a target width;
2. Contact glyphs, which are 0-dimensional points lying at grid points, e.g., used to describe vertical interconnections (contacts and vias). The attached properties of a contact glyph include which layer the contact belongs to, and parameters that specify how contacts are to be arranged in a matrix, e.g. the number of rows and columns in the matrix, the size of each contact, the horizontal and vertical distances between columns and rows, respectively and an optional offset of the matrix center relative to the glyph position; and
3. Area glyphs, which are 2-dimensional, axis aligned rectangles whose vertices are on grid points, e.g., used to describe diffusion regions. In addition to their specific attributes, glyphs can carry ‘design intent’ attributes, e.g. net names, ratings of their importance etc. A process called elaboration turns sets of glyphs into geometry (pre-data-prep mask shapes).
A pattern describes a glyph configuration, e.g., a contact glyph with certain properties sitting on a stick glyph with another set of properties. Elaboration creates shapes for this configuration based on a set of parameters, e.g., elaboration may create a pad on an M1 stick and four redundant vias on the pad. Given the computational complexity of converting glyph patterns into VLSI designs, the identification of predefined patterns is a key component of the elaboration process. Various aspects of elaboration are described in U.S. patent application PSEUDO-STRING BASED PATTERN RECOGNITION IN L3GO DESIGNS, Ser. No. 11/621,383, filed on Jan. 9, 2007, and U.S. patent application GRAPH-BASED PATTERN MATCHING IN L3GO DESIGNS, Ser. No. 11/623,541, filed on Jan. 16, 2007, (collectively referred to as “L3GO disclosures”), which are hereby incorporated by reference. In particular, these disclosures describe a process for matching patterns at a single or discrete hierarchical level.
One of the challenges of the elaboration process involves the fact that glyph patterns are essentially specified in a flat (i.e., two-dimensional) space, but L3GO designs and the produced VLSI designs are in the majority of cases described hierarchically. The major reason for using a hierarchical description is to hide the vast amount of detail in a design. By reducing the distracting detail to a single object that is lower in the hierarchy, one can greatly simplify many CAD (computer aided design) operations. For example, simulation, verification, design-rule checking, and layout constraints can all benefit from hierarchical representation, which makes them much more computationally tractable.
Since many circuits are too complicated to be easily considered in their totality, a complete design is often viewed as a collection of component aggregates that are further divided into subaggregates in a recursive and hierarchical manner. In VLSI design, these aggregates are commonly referred to as cells. The use of a cell at some point in a circuit implies that the entire content of the cell's definition is present at that point in the final circuit. Multiple uses of a cell indicate that the cell contents are to be repeated at each use. Graphically, an instance can be seen as an outline that displays only the boundary of the cell definition, or it can be displayed more fully by showing the cell's contents.
Accordingly, a need exists for a system and method that can apply flat pattern based L3GO elaboration in a hierarchical environment to create a nested conventional layout.